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25/0251
Static RAM with Sem, Int, Busy
CY7C024/0241 CY7C025/0251
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy
Features
* True Dual-Ported memory cells which allow simultaneous reads of the same memory location * 4K x 16 organization (CY7C024) * 4K x 18 organization (CY7C0241) * 8K x 16 organization (CY7C025) * 8K x 18 organization (CY7C0251) * 0.65-micron CMOS for optimum speed/power * High-speed access: 15 ns * Low operating power: ICC = 150 mA (typ.) * Fully asynchronous operation * Automatic power-down * Expandable data bus to 32/36 bits or more using Master/Slave chip select when using more than one device * On-chip arbitration logic * Semaphores included to permit software handshaking between ports * INT flag for port-to-port communication * Separate upper-byte and lower-byte control * Pin select for Master or Slave * Available in 84-pin PLCC and 100-pin TQFP * Pin-compatible and functionally equivalent to IDT7024/IDT7025
Functional Description
The CY7C024/0241 and CY7C025/0251 are low-power CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the CY7C024/0241 and CY7C025/0251 to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C024/0241 and CY7C025/0251 can be utilized as standalone 16-/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32-/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32-/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt Flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin. The CY7C024/0241 and CY7C025/0251 are available in 84-pin PLCCs (CY7C024 and CY7C025 only) and 100-pin Thin Quad Plastic Flatpack (TQFP).
Cypress Semiconductor Corporation Document #: 38-06035 Rev. **
*
3901 North First Street
*
San Jose
*
CA 95134 * 408-943-2600 Revised September 18, 2001
CY7C024/0241 CY7C025/0251
v
Logic Block Diagram
R/WL UB L R/WR UBR
LB L CE L OE L
LB R CE R OE R
I/O 8L - I/O 15L I/O 0L - I/O 7L
[3]
[2] [1]
I/O CONTROL
I/O CONTROL
I/O8R - I/O 15R [3] I/O 0R - I/O 7R
[1] [2]
BUSYL (CY7C025/0251)
A12L A11L A0L ADDRESS DECODER MEMORY ARRAY ADDRESS DECODER
BUSYR A12R (CY7C025/0251) A11R A 0R
CE L OE L UB L LB L R/W L SEM L INT L
INTERRUPT SEMAPHORE ARBITRATION
CE R OE R UB R LB R R/W R SEM R
7C024-1
M/S
INT R
Notes: 1. BUSY is an output in master mode and an input in slave mode. 2. I/O0 -I/O8 on the CY7C0241/0251. 3. I/O9 -I/O17 on the CY7C0241/0251.
Document #: 38-06035 Rev. **
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CY7C024/0241 CY7C025/0251
Pin Configurations
84-Pin PLCC Top View
SEM L CE L UB L GND I/O 1L I/O 0L OE L V CC LB L NC [4] A11L R/WL I/O 7L I/O 6L I/O 5L I/O 4L I/O 3L I/O 2L A 10L A A 8L A7L A6L A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R
9L
11 10 9 8 7 6 5 4 3 2 I/O8L I/O9L I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 SEMR CER UB R LB R NC [5] A 11R GND I/O15R OE R R/WR I/O 9R I/O 10R I/O 11R I/O 12R I/O13R I/O 14R GND A 10R A 9R A 8R A 7R
1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 CY7C024/5 65 64 63 62 61 60 59
7C024-1
OEL VCC R/WL SEML CEL
100-Pin TQFP Top View
UBL LBL NC [4] A11L A10L I/O4L I/O3L I/O2L GND I/O9L I/O8L I/O7L I/O6L I/O5L I/O1L I/O0L A9L A8L A7L A6L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC NC NC I/O10L I/O11L I/O12L I/O13L GND I/O14L I/O15L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC NC NC NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC NC NC
CY7C024/5
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 7C024-2 GND I/O15R OER I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R R/WR GND SEMR CER UBR LBR NC [5] A11R A10R A9R A8R I/O13R I/O14R A7R A6R A5R
Notes: 4. A12L on the CY7C025/0251. 5. A12R on the CY7C025/0251.
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CY7C024/0241 CY7C025/0251
Pin Configurations (continued)
OEL VCC R/WL SEML CEL
100-Pin TQFP Top View
I/O10L I/O9L I/O7L I/O6L I/O5L UBL LBL NC [4] A11L A10L I/O4L I/O3L I/O2L GND I/O1L I/O0L A9L A8L A7L A6L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC I/O8L I/O17L I/O11L I/O12L I/O13L I/O14L GND I/O15L I/O16L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R I/O8R I/O17R NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 NC NC NC NC A5L A4L A3L A2L A1L A0L INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R NC NC NC NC
CY7C0241/0251
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 7C024-3 I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R GND I/O16R OER R/WR GND SEMR CER UBR LBR I/O7R I/O9R NC [5] A11R A10R A9R A8R A7R A6R A5R
Pin Definitions
Left Port CEL R/WL OEL A0L-A11/12L I/O0L-I/O15/17L SEML UBL LBL INTL BUSYL M/S VCC GND CER R/WR OER A0R-A11/12R I/O0R-I/O15/17R SEMR UBR LBR INTR BUSYR Right Port Chip Enable Read/Write Enable Output Enable Address Data Bus Input/Output Semaphore Enable Upper Byte Select Lower Byte Select Interrupt Flag Busy Flag Master or Slave Select Power Ground Description
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CY7C024/0241 CY7C025/0251
Selection Guide
7C024/0241-15 7C025/0251-15 Maximum Access Time (ns) Typical Operating Current (mA) Typical Standby Current for ISB1 (mA) 15 190 50 7C024/0241-25 7C025/0251-25 25 170 40 7C024/0241-35 7C025/0251-35 35 160 30 7C024/0241-55 7C025/0251-55 55 150 20
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied.............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.3V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage[6] ........................................ -0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
7C024/0241-15 7C025/0251-15 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 ISB3 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Operating Current GND VI VCC Output Disabled, GND VO VCC VCC = Max., IOUT = 0 mA, Outputs Disabled Com'l Ind Com'l Ind Com'l Ind Com'l Ind Com'l Ind Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 4.0 mA 2.2 -0.7 -10 -10 190 200 50 50 120 120 3 3 110 110 0.8 +10 +10 300 320 70 70 180 180 15 15 160 160 100 100 3 3 90 90 Min. Typ. 2.4 0.4 2.2 -0.7 -10 -10 170 170 40 0.8 +10 +10 250 290 60 75 150 170 15 15 130 150 mA mA mA mA 7C024/0241-25 7C025/0251-25 Max. Unit V 0.4 V V V A A mA 2.4
Max. Min. Typ.
Standby Current CEL and CER VIH, (Both Ports TTL Levels) f = fMAX[7] Standby Current (One Port TTL Level) Standby Current (Both Ports CMOS Levels) Standby Current (Both Ports CMOS Levels) CEL or CER VIH, f = fMAX[7] Both Ports CE and CER VCC - 0.2V, VIN VCC - 0.2V or VIN 0.2V, f = 0[7] One Port CEL or CER VCC - 0.2V, VIN VCC - 0.2V or VIN 0.2V, Active Port Outputs, f = fMAX[7]
ISB4
Notes: 6. Pulse width < 20 ns. 7. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
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CY7C024/0241 CY7C025/0251
Electrical Characteristics Over the Operating Range (continued)
7C024/0241-35 7C025/0251-35 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 ISB3 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Operating Current Standby Current (Both Ports TTL Levels) Standby Current (One Port TTL Level) Standby Current (Both Ports CMOS Levels) Standby Current (Both Ports CMOS Levels) GND VI VCC VCC = Max., IOUT = 0 mA, Outputs Disabled CEL and CER VIH, f = fMAX[7] CEL or CER VIH, f = fMAX[7] Both Ports CE and CER VCC - 0.2V, VIN VCC - 0.2V or VIN 0.2V, f = 0[7] One Port CEL or CER VCC - 0.2V, VIN VCC - 0.2V or VIN 0.2V, Active Port Outputs, f = fMAX[7] Com'l Ind Com'l Ind Com'l Ind Com'l Ind Com'l Ind Output Leakage Current Output Disabled, GND VO VCC Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 4.0 mA 2.2 -0.7 -10 -10 160 160 30 30 85 85 3 3 80 80 0.8 +10 +10 230 260 50 65 135 150 15 15 120 135 Min. Typ. 2.4 0.4 2.2 -0.7 -10 -10 150 150 20 20 75 75 3 3 70 70 0.8 +10 +10 230 260 50 65 135 150 15 15 120 135 mA mA mA mA 7C024/0241-55 7C025/0251-55 Max. Unit V 0.4 V V V A A mA 2.4
Max. Min. Typ.
ISB4
Capacitance[8]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF
AC Test Loads and Waveforms
5V 5V R1 = 893 OUTPUT C = 30 pF R2 = 347 VTH = 1.4V
7C024-8 7C024-9
OUTPUT C = 30pF
RTH = 250 R1 = 893 OUTPUT C = 5 pF R2 = 347
7C024-10
(a) Normal Load (Load 1)
(b) Thevenin Equivalent (Load 1) ALL INPUT PULSES
(c) Three-State Delay (Load 3)
OUTPUT C = 30 pF
3.0V GND 10% 90%
90% 10%
3 ns
3 ns
7C024-12
Load (Load 2)
7C024-11
Note: 8. Tested initially and after any design or process changes that may affect these parameters.
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CY7C024/0241 CY7C025/0251
Switching Characteristics Over the Operating Range[9]
7C024/0241-15 7C025/0251-15 Parameter READ CYCLE tRC tAA tOHA tACE[10] tDOE tLZOE[11, 12, 13] tHZOE[11, 12, 13] tLZCE[11, 12, 13] tHZCE[11, 12, 13] tPU[13] tPD[13] tABE[10] tWC tSCE[10] tAW tHA tSA[10] tPWE tSD tHD tHZWE[12, 13] tLZWE[12, 13] tWDD[14] tDDD[14] Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power-Up CE HIGH to Power-Down Byte Enable Access Time Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold From Write End Address Set-Up to Write Start Write Pulse Width Data Set-Up to Write End Data Hold From Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid 0 30 25 15 12 12 0 0 12 10 0 10 0 50 35 0 15 15 25 20 20 0 0 20 15 0 15 0 60 35 3 10 0 25 25 35 30 30 0 0 25 15 0 20 0 70 45 3 10 3 15 0 25 35 55 35 35 0 0 35 20 0 25 3 15 10 3 15 3 20 0 55 55 15 15 3 25 13 3 20 3 25 25 25 3 35 20 3 25 35 35 3 55 25 55 55 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C024/0241-25 7C025/0251-25 Min. Max. 7C024/0241-35 7C025/0251-35 Min. Max. 7C024/0241-55 7C025/0251-55 Min. Max. Unit
WRITE CYCLE
Notes: 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH and 30-pF load capacitance. 10. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time. 11. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 12. Test conditions used are Load 3. 13. This parameter is guaranteed but not tested. 14. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
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CY7C024/0241 CY7C025/0251
Switching Characteristics Over the Operating Range[9] (continued)
7C024/0241-15 7C025/0251-15 Parameter BUSY TIMING tBLA tBHA tBLC tBHC tPS tWB tWH tBDD[16]
[15]
7C024/0241-25 7C025/0251-25 Min. Max. 20 20 20 20 5 0 20
7C024/0241-35 7C025/0251-35 Min. Max. 20 20 20 20 5 0 30
7C024/0241-55 7C025/0251-55 Min. Max. 45 40 40 35 5 0 40 Unit ns ns ns ns ns ns ns Note 16 30 30 20 15 15 ns
Description BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Set-Up for Priority R/W HIGH after BUSY (Slave) R/W HIGH after BUSY HIGH (Slave) BUSY HIGH to Data Valid
Min.
Max. 15 15 15 15
5 0 13 Note 16 15 15 10 5 5 15
Note 16 20 20 12 10 10 25 15 10 10
Note 16 25 25
INTERRUPT TIMING[15] tINS tINR tSOP tSWRD tSPS tSAA INT Set Time INT Reset Time SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window SEM Address Access Time ns ns ns ns ns 55 ns
SEMAPHORE TIMING
35
Notes: 15. Test conditions used are Load 2. 16. tBDD is a calculated parameter and is the greater of tWDD-tPWE (actual) or tDDD-tSD (actual).
Data Retention Mode
The CY7C024/0241 is designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention: 1. Chip enable (CE) must be held HIGH during data retention, within VCC to VCC - 0.2V. 2. CE must be kept between VCC - 0.2V and 70% of VCC during the power-up and power-down transitions. 3. The RAM can begin operation >tRC after VCC reaches the minimum operating voltage (4.5 volts).
Timing
Data Retention Mode VCC 4.5V VCC > 2.0V 4.5V tRC
V IH
CE
VCC to VCC - 0.2V
7C024-13
Parameter ICCDR1
Test Conditions @ VCCDR = 2V
[17]
Max. 1.5
Unit mA
Note: 17. CE = VCC, Vin = GND to VCC, TA = 25C. This parameter is guaranteed but not tested.
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CY7C024/0241 CY7C025/0251
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)[18, 19, 20]
tRC ADDRESS tOHA DATA OUT tAA DATA VALID
7C024-14
tOHA
PREVIOUS DATA VALID
Read Cycle No. 2 (Either Port CE/OE Access)[18,
CE and LB or UB OE
21, 22]
tACE tHZCE tDOE tHZOE tLZOE DATA VALID tLZCE tPU
DATA OUT
ICC CURRENT ISB
tPD
7C024-15
Read Cycle No. 3 (Either Port)[18, 20, 21,
21, 22]
tRC ADDRESS tAA UB or LB tHZCE tLZCE tABE CE tACE tLZCE DATA OUT tHZCE tOHA
7C024-16
Notes: 18. R/W is HIGH for read cycles 19. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 20. OE = VIL. 21. Address valid prior to or coincident with CE transition LOW. 22. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL.
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CY7C024/0241 CY7C025/0251
Switching Waveforms (continued)
Write Cycle No. 1: R/W Controlled Timing[23, 24, 25, 26]
tWC ADDRESS tHZOE [29] OE tAW CE
[27,28]
tSA R/W tHZWE[29] DATA OUT
tPWE[26]
tHA
tLZWE
NOTE 30
tSD tHD
NOTE 30
DATA IN
7C024-17
Write Cycle No. 2: CE Controlled Timing[23, 24, 25, 31]
tWC ADDRESS tAW CE
[27,28]
tSA R/W
tSCE
tHA
tSD DATA IN
tHD
7C024-18
Notes: 23. R/W must be HIGH during all address transitions. 24. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB. 25. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 26. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 27. To access RAM, CE = VIL, SEM = VIH. 28. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 29. Transition is measured 500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested. 30. During this period, the I/O pins are in the output state, and input signals must not be applied. 31. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
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CY7C024/0241 CY7C025/0251
Switching Waveforms (continued)
Semaphore Read After Write Timing, Either Side[32]
tAA A 0-A 2 VALID ADRESS tAW SEM tSCE tSD I/O 0 tSA R/W tSWRD OE WRITE CYCLE tSOP READ CYCLE
7C024-19
tOHA
VALID ADRESS tACE tSOP
tHA
DATAIN VALID tPWE tHD
DATAOUT VALID
tDOE
Timing Diagram of Semaphore Contention[33, 34, 35]
A0L -A 2L
MATCH
R/WL SEM L tSPS A 0R -A 2R MATCH
R/WR SEM R
7C024-20
Notes: 32. CE = HIGH for the duration of the above timing (both write and read cycle). 33. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 34. Semaphores are reset (available to both ports) at cycle start. 35. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
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CY7C024/0241 CY7C025/0251
Switching Waveforms (continued)
Timing Diagram of Read with BUSY (M/S=HIGH)[36]
tWC ADDRESS R R/WR MATCH tPWE
tSD DATA INR tPS ADDRESS L MATCH tBLA BUSY L tDDD DATA OUTL tWDD VALID
tHD
tBHA tBDD
VALID
7C024-21
Write Timing with Busy Input (M/S=LOW)
R/W tWB tPWE
BUSY
tWH
7C024-22
Note: 36. CEL = CER = LOW.
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CY7C024/0241 CY7C025/0251
Switching Waveforms (continued)
Busy Timing Diagram No.1 (CE Arbitration)[37] CELValid First:
ADDRESS L,R CEL tPS CER tBLC BUSYR
7C024-23
ADDRESS MATCH
tBHC
CER ValidFirst:
ADDRESS L,R CER tPS CE L tBLC BUSY L
7C024-24
ADDRESS MATCH
tBHC
Busy Timing Diagram No.2 (Address Arbitration)[37] Left Address Valid First
tRC or tWC ADDRESS L ADDRESS MATCH tPS ADDRESS R tBLA BUSY R
7C024-25
ADDRESS MISMATCH
tBHA
Right Address Valid First:
tRC or tWC ADDRESS R ADDRESS MATCH tPS ADDRESS L tBLA BUSY L
7C024-26
ADDRESS MISMATCH
tBHA
Note: 37. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
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CY7C024/0241 CY7C025/0251
Switching Waveforms (continued)
Interrupt Timing Diagrams Left Side Sets INTR :
ADDRESS L CE L R/W L INT R tINS [39]
7C024-27
tWC WRITE FFF (1FFF CY7C025) tHA[38]
Right Side Clears INT R :
ADDRESSR CE R tINR [39] R/WR OE R INTR
tRC READ FFF (1FFF CY7C025)
7C024-28
Right Side Sets INT L:
tWC ADDRESSR CE R WRITE FFE (1FFE CY7C025) tHA[38]
R/W R INT L tINS
[39]
7C024-29
Left Side Clears INT L:
ADDRESS R CE L tINR[39] R/W L OE L INT L
tRC READ FFE (1FFE CY7C025)
7C024-30
Notes: 38. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 39. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
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CY7C024/0241 CY7C025/0251
Architecture
The CY7C024/0241 and CY7C025/0251 consist of an array of 4K words of 16/18 bits each and 8K words of 16/18 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the CY7C024/0241 and CY7C025/0251 can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The CY7C024/0241 and CY7C025/0251 have an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. tention). If both ports' CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but which one is not predictable. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Master/Slave A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA). Otherwise, the slave chip may begin a write cycle during a contention situation.When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C024/0241 and CY7C025/0251 provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0-2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 shows sample semaphore operations. When reading a semaphore, all sixteen/eighteen data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
Functional Description
Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user of the CY7C024/0241 or CY7C025/0251 wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (FFF for the CY7C024/0241, 1FFF for the CY7C025/0251) is the mailbox for the right port and the second-highest memory location (FFE for the CY7C024/0241, 1FFE for the CY7C025/0251) is the mailbox for the left port. When one port writes to the other port's mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port's mailbox without resetting the interrupt. The active state of the BUSY signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active BUSY to a port prevents that port from reading its own mailbox and thus resetting the interrupt to it. If your application does not require message passing, do not connect the interrupt pin to the processor's interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2. Busy The CY7C024/0241 and CY7C025/0251 provide on-chip arbitration to resolve simultaneous memory location access (conDocument #: 38-06035 Rev. **
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CY7C024/0241 CY7C025/0251
Table 1. Non-Contending Read/Write Inputs CE H X L L L L L L X H X H X L L X X R/W X X L L L H H H X H H OE X X X X X L L L H L L X X X X UB X H L H L L H L X X H X H L X LB X H H L L H L L X X H X H X L SEM H H H H H H H H X L L L L L L High Z High Z High Z Data In Data In High Z Data Out Data Out High Z Data Out Data Out Data In Data In Outputs I/O0-I/O7[2] I/O8-I/O15[3] High Z High Z Data In High Z Data In Data Out High Z Data Out High Z Data Out Data Out Data In Data In Operation Deselected: Power-Down Deselected: Power-Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled Read Data in Semaphore Flag Read Data in Semaphore Flag Write DIN0 into Semaphore Flag Write DIN0 into Semaphore Flag Not Allowed Not Allowed
Table 2. Interrupt Operation Example (assumes BUSYL=BUSYR=HIGH)[40] Left Port Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag Table 3. Semaphore Operation Example Function No action Left port writes 0 to semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore
Notes: 40. A0L-12L and A0R-12R, 1FFF/1FFE for the CY7C025. 41. If BUSYR=L, then no change. 42. If BUSYL=L, then no change.
Right Port INTL X X L[41] H
[42]
R/WL L X X X
CEL L X X L
OEL X X X L
A0L-11L (1)FFF X X (1)FFE
R/WR X X L X
CER X L L X
OER X L X X
A0R-11R X (1)FFF (1)FFE X
INTR L[42] H[41] X X
I/O0-I/O15/17 Left 1 0 0 1 1 0 1 1 1 0 1
I/O0-I/O15/17 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free
Status Left Port has semaphore token No change. Right side has no write access to semaphore. Right port obtains semaphore token No change. Left port has no write access to semaphore Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free
Document #: 38-06035 Rev. **
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CY7C024/0241 CY7C025/0251
Ordering Information
4K x16 Dual-Port SRAM Speed (ns) 15 25 Ordering Code CY7C024-15AC CY7C024-15JC CY7C024-25AC CY7C024-25JC CY7C024-25AI CY7C024-25JI 35 CY7C024-35AC CY7C024-35JC CY7C024-35AI CY7C024-35JI 55 CY7C024-55AC CY7C024-55JC CY7C024-55AI CY7C024-55JI 8K x 16 Dual-Port SRAM Speed (ns) 15 Ordering Code CY7C025-15AC CY7C025-15JC CY7C025-15AI 25 CY7C025-25AC CY7C025-25JC CY7C025-25AI CY7C025-25JI 35 CY7C025-35AC CY7C025-35JC CY7C025-35AI CY7C025-35JI 55 CY7C025-55AC CY7C025-55JC CY7C025-55AI CY7C025-55JI Package Name A100 J83 A100 A100 J83 A100 J83 A100 J83 A100 J83 A100 J83 A100 J83 Package Type 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Industrial Industrial Commercial Operating Range Commercial Package Name A100 J83 A100 J83 A100 J83 A100 J83 A100 J83 A100 J83 A100 J83 Package Type 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flat Pack 84-Lead Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Industrial Commercial Operating Range Commercial
Document #: 38-06035 Rev. **
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CY7C024/0241 CY7C025/0251
4K x 18 Dual-Port SRAM Speed (ns) 15 25 35 55 Ordering Code CY7C0241-15AC CY7C0241-15AI CY7C0241-25AC CY7C0241-25AI CY7C0241-35AC CY7C0241-35AI CY7C0241-55AC CY7C0241-55AI Package Name A100 A100 A100 A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
Ordering Information (continued)
8K x 18 Dual-Port SRAM Speed (ns) 15 25 35 55 Ordering Code CY7C0251-15AC CY7C0251-25AC CY7C0251-25AI CY7C0251-35AC CY7C0251-35AI CY7C0251-55AC CY7C0251-55AI Package Name A100 A100 A100 A100 A100 A100 A100 Package Type 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack 100-Pin Thin Quad Flat Pack Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial
Document #: 38-06035 Rev. **
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CY7C024/0241 CY7C025/0251
Package Diagrams
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-A
84-Lead Plastic Leaded Chip Carrier J83
51-85006-A
Document #: 38-06035 Rev. **
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(c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C024/0241 CY7C025/0251
Document Title: CY7C024/0241, CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy Document Number: 38-06035 REV. ** ECN NO. 110177 Issue Date 09/29/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00255 to 38-06035
Document #: 38-06035 Rev. **
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